SBIR/STTR Research Award
Nano-Device Memory Platform (NDMP)
Award amount
$119,789Program and phase
SBIR · Phase IAward year
2007Award details
- Awarding agency
- Department of Defense
- Branch
- Army
- Recipient company
- Privatran, LLC
- Proposal award date
- 2007-11-07
- Contract end date
- 2008-05-05
- UEI
- GMG1QFG3GS35
- Solicitation number
- 2007.2
- Topic code
- A07-061
Research abstract
The Phase I program will demonstrate the feasibility and the initial design specifications for integrating nano-device switching elements with the available silicon crossbar array technology. Here, the minimum goal is memory arrays that are scaleable to 1010 bits/cm2 for pseudo non-volatile memory based on the silicon-molecule hybrid systems. Preliminary fabrication and testing will demonstrate read-write-erase function over 1000 cycles with 60 minutes of non-volatility
Technology keywords
Not reported
Other awards by this recipient
Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.
- Low Power Nonvolatile Memory for Extreme Environments
- Multi Band SAL Seeker Read Out Integrated Circuit (ROIC)
- Low-Cost Radiation-Hard Nonvolatile Random-Access Memory
- Low-Cost Radiation-Hard Nonvolatile Random-Access Memory
- Wavefront/ Wavefunction Sensor for 3D Imaging
Awards with the same topic code
Verified by an exact topic code match. This is not a text-similarity match.
- Self-Assembly Production of Hybrid CMOS/Nanodevice Interconnects
- Nano-Device Memory Platform (NDMP)
- Self-Assembly Production of Hybrid CMOS/Nanodevice Interconnects
Research funding history
15 SBIR/STTR records share this UEI (2007–2014). Reported award amounts total $4,264,321. Reported amounts are not federal obligations.
Phases: Phase I, Phase II
Agencies: Department of Defense, National Science Foundation, National Aeronautics and Space Administration