Prognostic for Process-Related Integrated Circuits (IC)

This SBIR is to design, develop, fabricate and package a suite of Integrated Circuit (IC) sensors as an IC chip. The chip, referred to as IC Prognostics chip, will contain four groups of sensors to sense damage to the “canary” devices on the IC chip: a damaged canary indicates a high probability of similar damage to like devices on an electronic assembly. There are three variations of IC Prognostics, each targeted for specific IBM CMOS process nodes: 130 nm, 90 nm and 65 nm. The targeted failure modes are (1) Hot Carrier, (2) Electrostatic Damage, (3) Time Dependent Dielectric Breakdown, (4) Voltage Threshold shift, (5,6) Total Dose Ionization effects on VT and Leakage Current, (7) Resistor value change and (8) Capacitor value change. The SBIR also calls for each IC Prognostic chip to have a 1-bit serial data output capability. Optionally, each IC Prognostic chip would have a hardware I2C-bus interface for military application use such as the Joint Strike Fighter.