Nanostructures for dislocation blocking in infrared detectors

HgCdTe is the material of choice for the fabrication of high performance infrared focal plane arrays. HgCdTe is usually grown on CdZnTe substrates, which suffer from cost and size limitations. Silicon substrates do not have these constraints. Although device-quality HgCdTe cannot be grown directly on silicon, a CdTe buffer layer allows its growth. However, large lattice and thermal mismatches between CdTe and silicon lead to a high density of dislocations. These mismatches are clearly impeding advances in HgCdTe focal plane array technology. To mitigate these issues, we propose a novel approach to fabricate nanostructured CdTe buffer layers on silicon substrates and achieve the selective epitaxy of CdTe followed by epitaxial lateral overgrowth. Novel defect reduction mechanisms are available when the substrate pattern dimensions are reduced to the nanoscale. In the proposed Phase I program, we will explore the feasibility of dislocation reduction with nanopatterned CdTe/Si buffer layers. We will also perform MBE growth on nanopatterned silicon on insulator substrates to compare the defect formation mechanisms on both substrate types. The ultimate goal of this project is to produce LWIR HgCdTe/CdTe/Si layers that rival the quality of HgCdTe/CdZnTe ones without the cost and size drawbacks associated with the use of CdZnTe.