An FPGA-based Algorithm Accelerator for High-Performance Navy Laptop and Workstation Environments

Rydal Research proposes to research and demonstrate the feasibility of developing an FPGA-based Algorithm Accelerator for high-performance Navy applications. The accelerator will be developed using Rydal’s automated algorithm-to-hardware design system. This system quickly produces VHDL designs guaranteed to be optimized in terms of characteristics such as speed, size, power, or any combination of these. The design system will be used to generate a large number of different hardware/software partitioning schemes and to perform detailed hardware designs to obtain accurate speed, size, and power predictions. The system is capable of easily translating large, complex designs and it is also able to partition the application over multiple FPGAs. The rapid design process will allow critical parts of candidate designs to be ported to an actual FPGA and demonstrated in Phase I to verify hardware simulation predictions.