SBIR/STTR Research Award

Prognostic Capabilities for Field Effect Transistors (FET)

Award identifier b9a65b37c23dbebce1a52ad138f4a0ee4d2cdcedc4f7275a8d9ac16ba61bc13dAwarding agency Department of Defense · Navy

Award amount

$1,001,800

Program and phase

SBIR · Phase II

Award year

2007

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Award details

Awarding agency
Department of Defense
Branch
Navy
Recipient company
RIDGETOP GROUP INC
Proposal award date
2007-04-12
Contract end date
2009-04-12
UEI
CRLUWHJZHLU8
Solicitation number
2006.1
Topic code
N06-007

Research abstract

Shrinking semiconductor process geometries (130 nm and below) are increasingly subject to performance, lifetime, and reliability-limiting effects that can cause hard-to-diagnose intermittent failures. One of the most serious emerging reliability problems is called Negative Bias Temperature Instability (NBTI). NBTI is a p-MOSFET degradation mechanism that causes increasing threshold voltage (VT) shifts. Such shifts, if large enough, cause intermittent performance problems in electronic modules, including timing errors and gain accuracy errors. Working with IBM’s Trusted Foundry semiconductor process, Ridgetop will design, develop, and fabricate an NBTI prognostic circuit that measures the VT shift in a p-MOSFET and reports its state-of-health. The p-FET Prognostic Chip will be fabricated in the IBM 130 nm process, with Options for the IBM 90 nm and 65 nm processes. Ridgetop will also provide generic serial data output capability, and as an Option, an I2C-bus interface for use in important military applications, such as the Joint Strike Fighter.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Agency intelligence

Department of Defense

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