SBIR/STTR Research Award
High Data Rate, Low Power Analog to Digital Converter
Award amount
$99,912Program and phase
SBIR · Phase IAward year
2007Award details
- Awarding agency
- Department of Defense
- Branch
- Air Force
- Recipient company
- TIALINX, INC.
- Proposal award date
- 2006-12-15
- Contract end date
- 2007-12-14
- UEI
- DN5XPZUDBMN6
- Solicitation number
- 2006.3
- Topic code
- AF063-004
Research abstract
In response to the phase I SBIR proposal, various methods of using flash and folding analaog to digital conversion designs have been proposed to address feasibility of design of an ADC with the minimum requirement of: ERBW > 1 GHz (sample rate >2 GSPS), ENOB >10 bits, Power dissipation 1 Mrad, Operating temperature range –40 to +80 deg C Gain flatness 80 dB. Favorable process technologies and devices have been elaborated.
Technology keywords
Not reported
Other awards by this recipient
Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.
- Handheld Hidden Chamber Detection
- Electronically Controlled Adaptive Polarization for Compact Broadband Transmitters and Receivers
- Handheld Hidden Chamber Detection
- Electronically Controlled Adaptive Polarization for Compact Broadband Transmitters and Receivers
- Chip-Scale Technologies for Giga-band Signals
Awards with the same topic code
Verified by an exact topic code match. This is not a text-similarity match.
Research funding history
20 SBIR/STTR records share this UEI (2004–2020). Reported award amounts total $9,206,766. Reported amounts are not federal obligations.
Phases: Phase I, Phase II
Agencies: Department of Defense, National Science Foundation