High Speed Memory Management Unit

The rapid advancement in various electronics systems (imaging, radar, SIGINT, etc.) demand a high speed data transfer and storage techniques. Limitations in data bus bandwidth and data storage mediums have become bottlenecks to progress in various disciplines. An affordable, high-bandwidth data capture box utilizing the most recent developments in commercial electronics is proposed. The limiting factors of any high bandwidth storage system are the interface between memory and processor. We propose to extend the performance of commercially available high speed data link devices using techniques such as modularization and parallelization to achieve aggregate transmission rates of 1Tbit/s and storage densities of 10-100Tbits. Our Phase I objectives are to perform requirements analysis and derive design specifications in the light of requirements, component availability, and cost. Once the design specifications are derived, we shall perform a preliminary system design and perform simulation to obtain the performance characteristics. Based on these simulations and analysis a scalable prototype memory management unit will be manufactured and benchmarked. Analysis will be performed to identify any enhancements to be incorporated in the architecture during Phase II.