Large-Area Hybrid Substrates for HgCdTe Infrared Detectors

The Silicon Photonics Group at Arizona State University, Raytheon Vision Systems and NVESD propose new approaches to buffer layer architectures for integration of HgTe-CdTe (MCT) with Si. The Ge-Sn compositional range will be explored to fabricate lattice-engineered templates on various Si crystallographic orientations for the subsequent growth of CdTe at conditions compatible with Si CMOS processing. Silicon will also be incorporated into Ge-Sn to obtain Si-Ge-Sn ternaries that will provide tunable thermal matching with the II-VI compounds. The unique ability of the Si-Ge-Sn system to absorb defects and minimize strain in mismatched heteroepitaxy is likely to yield device quality materials with defect densities less than 105 cm-2. Growth, characterization and performance evaluation of HgCdTe will be conducted on CdTe/Ge1-xSnx/Si large-area (3-4”) low-cost substrates. Optimized CdTe/HgCdTe heterostructures will be used to produce and test prototype LWIR photodiodes and focal plane arrays in hybridized form. The objective is to demonstrate high performance MCT photodiodes grown on Si-Ge-Sn buffered Si that exceed base line characteristics of commercially available HgCdTe devices grown on Si(211). The uniqueness of this project lies on the development of entirely new classes of Si-based Si-Ge-Sn alloys with adjustable lattice constants and thermal expansion coefficients compatible with those of Hg-Cd-Te systems.