Secure Trusted Computing System-on-Chip

This SBIR Phase 1 project proposes the feasibility study of secure trusted computing System-on-Chip. To prevent or delay the compromise of Critical Program Information, DoD is seeking operational embedded technology to provide the real-time encryption and authentication and "other" capabilities for protecting and processing information in tactical systems. Also, technology shall detect tampering of the element and Zeroize mission critical information to deter reverse engineering efforts. One avenue worth exploring to this end is the development of the secure trusted system-on-chip (SOC). Using a superset of Trusted Computing Group TPM standard logic embedded with a 32 bit RISC processor and collateral interfaces, a trusted SOC would provide a feasible solution to this need-which would also include a streaming encryption capability, and universal I/O for easy utilization. The trusted SOC would be embedded to secure a given system with anti-tamper capabilities. Our anti-tamper circuits will be all digital making the design portable across different foundries and processes. Our multi-layered approach to security protects against single point of failure thus making it extremely difficult to extract information, especially if the attacker has access to only a few chips. A concept design specification will be delivered at the conclusion of the project.