Back Illuminated CMOS Detector Arrays

CMOS image sensors offer advantages for scientific and military applications, and although technology scaling benefits CMOS imagers by reducing pixel size, reducing power, and increasing each chips transistor density, today’s sub-micron CMOS technology is not directly suitable for designing high-quality image sensors. Furthermore, the CCD back-thinning processes don’t routinely transfer CMOS and many have had disappointing results backside thinning CMOS chips. In practice, the materials forming CMOS imagers from a range of manufacturers are all highly stressed mechanically, particularly in respect to the silicon layers of the device. This may result from the numerous metal and dielectric layers that characterize the modern CMOS imager. Working within the constraints of the ITRS roadmap, using a commercial foundries and standard equipment and processes, we will demonstrate two methods of back-thinning CMOS imagers, reliably and with low cost. Also in Phase I a monolithic back-illuminated CMOS imager design that can be fabricated using industry-standard tools in contemporary deep-sub-micron CMOS fabs will be detailed. Technology demonstrators will be fabricated to demonstrate the proof-of-concept, and the manufacturing process flow necessary to build a proof-of-concept science grade, back-illuminated CMOS imager in Phase II will be developed.BENEFITS: Three-dimensional, or stacked, semiconductors promise dramatic performance gains simply by arranging chip functions vertically, like the floors of a building. Stacked ICs have a wide range of applications including compact digital cameras, portable devices such as phones and PDAs, aerospace circuits, and the variety of commercial imaging applications.