Solid-state LIDAR Chip

A Solid-State Imaging LIDAR (SSIL) receiver for the AN/AES-1 and AN/AQS-20A mine detection systems will be designed, fabricated, tested, and demonstrated. Each of the SSIL’s 1024 signal channels tightly couples a highly-sensitive APD with a wide-bandwidth, low-noise amplifier, and high-sample-rate analog wavefront storage register. The high-performance, monolithic, CMOS LIDAR receiver benefits from silicon’s high, 532 nm quantum efficiency and its low avalanche multiplication noise. Monolithically integrating the SSIL’s photodetector, amplifier, and sampling circuits in a single CMOS chip eliminates bond and solder connections, lowers parasitic capacitance, reduces noise, and increases bandwidth. The shorter connection between the photodiode and amplifier increases the receiver’s immunity to electromagnetic interference. The elimination of the bond and solder connections means less fault liability, easier assembling processes, and reduced chip area. Thus, the size and weight of receiver is reduced. In the program’s first year, a fully-functional SSIL array will be designed and each of the critical CMOS circuits will be fabricated and characterized. In year two, the fully-integrated, monolithic SSIL receiver will be fabricated and tested. In an optional Phase II task, reliability and environmental testing will be performed to demonstrate the SSIL receiver’s technology readiness level and to aide its transition to the fleet.