SBIR Phase II: Liquid-Enabled Advanced Pitch (LEAP) Semiconductor Manufacturing

The broader/commercial impact of this Small Business Innovation Research (SBIR) Phase II project is the significant enhancement of domestic semiconductor manufacturing capabilities using existing lithography equipment and foundries. This project addresses the industry’s need for cost-effective, high-density semiconductor production without substantial capital investment in Extreme Ultraviolet (EUV) tools. The proposed process takes a photoresist pattern through a series of conventional track process steps to double the density of the original pattern. This technology enables existing fabrication facilities to produce significantly smaller semiconductor features (10–50 nm), enhancing their competitiveness and extending the lifespan of equipment. Consequently, this innovation has the potential to drastically reduce dependency on foreign semiconductor supply chains, enhance national manufacturing resilience, and lower barriers to entry for domestic customers. The capability to effectively manufacture high-density semiconductors at lower costs will transform essential sectors like artificial intelligence, quantum computing, and any devices linked to the Internet of Things (IoT). Additionally, our semiconductor overcoats will be formulated without Poly-and Perfluoroalkyl Substances (PFAS), persistent and ubiquitous environmental contaminants that increasingly concern scientists and regulatory agencies. Eliminating a source of PFAS in semiconductor manufacturing processes will help reduce environmental pollution, enhance public health, and support broader sustainability goals. This Small Business Innovation Research (SBIR) Phase II project aims to finalize and scale the materials for our innovative semiconductor manufacturing process, focusing on enabling sub-60 nm feature pitches with standard 193 nm lithography equipment. The project’s objectives include optimizing materials and processes tailored to specific customer needs, scaling production from lab-scale to pilot-scale volumes, and demonstrating robust manufacturing across multiple fabrication environments. The Phase II project will develop and validate the next-generation materials and process, applying advanced predictive modeling to provide guidance on selecting the optimal material combinations. Key technical outcomes expected include achieving competitive space width roughness (SWR), high critical dimension uniformity (CDU), and low pitch walking. Successful Phase II will engage with customers by shipping pint-level quantities of the Gen 2 materials for proof-of-concept demonstrations, gathering essential customer feedback to refine the materials, and establishing pathways for external funding and strategic partnerships. Additionally, the Phase II project will focus on Gen 3 materials compatible with EUV lithography, aiming to push feature miniaturization below 40 nm pitches. This effort will demonstrate the long-term viability and flexibility of our technology to address future lithography needs and position the materials for broader adoption in the semiconductor industry. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.