SBIR/STTR Research Award
Innovative Hardware Anti-Tamper Techniques
Award amount
$69,997Program and phase
SBIR · Phase IAward year
2005Award details
- Awarding agency
- Department of Defense
- Branch
- Army
- Recipient company
- SABRETEL
- Proposal award date
- 2005-02-02
- Contract end date
- 2005-08-02
- UEI
- Not reported
- Solicitation number
- 2004.3
- Topic code
- A04-169
Research abstract
SabreTel is developing an innovative embedded SecureRISC processor. The SabreTel SecureRISC Processor architecture is being developed to protect embedded application object code from being reverse engineered, detect any hacker attempts to tamper with the code, and take specific action as specified by the system designer when tampering is detected. The SecureRISC will be based on state-of-the-art computer architecture. The SabreTel SecureRISC will provide anti-tamper protection by executing AES encrypted opcodes. All object code external to the processor chip will be encrypted using the AES algorithm. Each instance of the encrypted object code will be different as a result of using the AES algorithm and a different key. Hackers will have a very difficult time reverse engineering the application code and determining in real time what the processor code is doing. Further, by executing object code in a modern cache architecture the hacker will not be able to tell what instruction in the cache is being executed by the processor. The innovative SecureRISC architecture provides three layers of security, of which without any one the embedded system is disabled: 1.) opcode encrypted application program, 2.) AES key, and 3.) hardware opcode decryption engine.
Technology keywords
Not reported
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