Hyper-thinning of Si for advanced 3-D memory stacking

This phase I SBIR proposal addresses development of a generalized benign, high throughput, low-cost silicon die thinning etch tool. Thinning of Si dies is required in many advanced 3-D packaging, rad-hard and flexible-circuit electronics. For example, using hyper-thin (~ 10-25 m) Si memory dies, a stack of 500 MCMs/inch can be formed to provide ~ 200 gigabits/cu. in. density using 64 mbits Si memory technology. Hyper-thin Si dies are of limited utility unless a benign thinning process applicable to conventional Si chips attached to an interconnect substrate can be developed. We have developed plasmaless XeF2 etch systems capable of creating hyper-thin Si layers without damaging the front surface electronic circuits. Extension of this system to multiwafer capability and cost-reduction through alternate source materials is addressed. Phase I research will be done in collaboration with GE Global Research Incorporated. Pathway to commercialization is identified through manufacturing of multiwafer etch tool in partnership with GE.