SBIR/STTR Research Award

Monolithic technology for Wafer Scale Phased Arrays

Award identifier fc6b42ec11f5bde54850c3c1858252436a7f71105d74549bb8ad9bbae3aab2d0Awarding agency Department of Defense · Defense Advanced Research Projects Agency

Award amount

$98,838

Program and phase

SBIR · Phase I

Award year

2004

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Award details

Awarding agency
Department of Defense
Branch
Defense Advanced Research Projects Agency
Recipient company
OPEL
Proposal award date
2004-11-29
Contract end date
2005-07-31
UEI
Not reported
Solicitation number
2004.3
Topic code
SB043-047

Research abstract

Phased arrays are critical for locating and tracking. Current TR modules use multiple MMIC chips, ferrite circulators and quasi-optical true-time-delay (TTD). Chip integration is not possible and interconnecting with GHZ RF outputs is a complicated board problem with little scalability to higher bandwidth, smaller size and lower power. OPEL proposes a monolithic IC solution based upon novel optoelectronic (OE) thryistor circuit design. Thyristor/HFET circuits implement TTD without a physical delay line and a novel power amplifier with a thyristor as an OE oscillator driving a Class E output. The receive channel is implemented with a thyristor LNA/mixer to achieve down-conversion with gain which is digitized with a new ƒA-ƒ' modulator. A thyristor based ripple counter implements a serializer circuit and produces the inverse TTD function for return signals without a physical delay line. Both T and R channels are integrated using a novel dielectric isolation. Optical and RF signal paths are maximized and minimized respectively to achieve a dramatic reduction in size weight and loss. As a monolithic circuit, wafer scale interconnect is implemented with a single interconnect mask. A 3¡" GaAs wafer can produce an array of about 16x16 integrated modules. OPEL will demonstrate this wafer scale integration

Technology keywords

Not reported

Awards with the same topic code

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Agency intelligence

Department of Defense

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