Dynamic Instruction Set Reconfigurable Processor for Software Protection

Software security - during every phase of development and deployment - is a mission-critical concern for all electronic systems. In Phase I, GateChange developed a cycle-accurate simulator of the Dynamic-Routing Array Processor (DRAP) and demonstrated the exceptional security (1.08x10901 encryption permutations) and performance of this architecture. The simulator was modeled on the actual silicon process selected for Phase II prototypes (design is 40% complete), insuring success in the ultimate device fabrication. DRAP consists of an array of processor cores and supporting, peripheral functions. Optimized communication paths between these elements are established in real-time, allowing highly efficient use and re-use of these resources. Additionally, DRAP implements variable-length, multi-dimensional hardware encryption chains that provide custom encryption for every individual word of code/data, protecting the software and overall system. DRAP can simultaneously operate as a streaming encryption/decryption engine, independent of the processor cores. DRAP's high-level (C/C++) design methodology eliminates cumbersome hardware description level designs, dramatically reducing development cycles. Development can be compartmentalized; different design teams can securely design for separate or even overlapping sections of the array. Furthermore, system life can be extended through in-field upgrades. DRAP's size, power, cost, high-performance, ease-of-use and security features create an excellent platform for a wide range of applications.