Asynchronous Component Interconnect Protocol

Theseus Logic, Inc. proposes a plug and play peripheral interconnect protocol that protects against obsolescence by using an asynchronous approach that does not rely on a specific clock rate. Additionally, an asynchronous approach provides robustness and flexibility that allows the same protocol used for a mezzanine bus to be applied to a peripheral bus. For this program, Theseus will apply their experience in chip level asynchronous interconnect techniques to the system level to develop a full featured interconnect architecture. This architecture will include the ability to support hardware information needed to maintain and calibrate the device, as well as version, manufacturer, description, and other data. Compatibility with current protocols will be retained to support legacy hardware.