HyperSpectral Data Cube Processor

We propose to implement a Hyperspectral Cube Processor by prototyping it on a set of innovative proprietary FPGA (Field Programmable Gate Array) boards which will lead to a highly compact, maximally parallel design. The proven design will be transferred to ASICs (Application Specific Integrated Circuits) in the Phase II program. Along with compactness and parallelization, we will be working toward maximal scalability e.g. the ability to expand for higher data traffic and for more complex operations by just adding more of similar modules, without major reorganization. In the FPGA prototype, we will use a mesh architecture (i.e. with all chips or boards inter-connected in a complete graph) with a serial, 10 Giga-bit/sec mesh backplane. The processor will employ our proprietary technology of massively parallel algorithms in hardware programming. The ultimate goal of the design is to distribute the Hyperspectral Image Processing between the inter-connected ASICs of the Processor in the most efficient way, thus providing the most compact device given the data traffic volume.