Mixed Signal MMIC for 10GHz Multifunction Frequency Syntheses and Modulations

This proposal presents an innovative, affordable, and feasible architecture of frequency synthesis and modulation based on SiGe high-speed MMIC designs. The architecture includes an ultrahigh-speed direct digital synthesizer (DDS) with a maximum clock frequency of 10GHz to synthesize and modulate the intermediate frequency (IF) of 1GHz and above. It uses a low-noise phase lock loop (PLL) to generate both the DDS clock and the carrier frequency of 10GHz and above. The PLL synthesizer includes a quadrature voltage controlled oscillator (VCO) to generate the quadrature carriers without using a high loss and narrow-band poly-phase network. The high-speed DDS includes a patent pending high-order delta-sigma noise shaper and a sinusoidal weighted digital-to-analog converter (DAC) with 15-bit resolution to achieve better than -60dB spectral purity. The cosine weighted DAC eliminates the sine and cosine look-up table, which is a speed and area bottleneck for high-speed DDS implementations. The DDS modulation waveform configurations include chirp, step frequency, FM, MSK, PM, AM, QAM, and other hybrid modulations. The modulated IF frequency is mixed with the carrier frequency using quadrature mixers with image rejection. The proposed architecture can be implemented in high-speed SiGe processing. Some critical blocks have been implemented and fabricated using IBM 5HP SiGe.