SBIR/STTR Research Award

SBIR Phase II: An Ultra-High-Speed Cleaning Process for Electronic Device Manufacturing

Award identifier 1092838705c999d996d9cb57e7072e1661dcec143bd3bb42b478ed68594c1499Awarding agency National Science Foundation

Award amount

$499,992

Program and phase

SBIR · Phase II

Award year

2005

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Award details

Awarding agency
National Science Foundation
Branch
Not reported
Recipient company
Phifer Smith Corporation
Proposal award date
Not reported
Contract end date
Not reported
UEI
Not reported
Solicitation number
Not reported
Topic code
Not reported

Research abstract

This Small Business Innovation Research (SBIR) Phase II project will develop process technology for removing photoresist from semiconductor wafers at high speed while not damaging underlying materials. This process technology can be readily integrated into existing single wafer wet processing tools. The development of higher performance semiconductor devices with smaller feature sizes has driven the adoption of copper and low-k dielectric materials that are susceptible to damage by traditional oxygen plasma based resist removal processes. While other low temperature plasma processes are being explored as low damage alternatives, appreciably lower resist removal rates (1,000 to 2,000 A /min) are a significant limitation. In response to this challenge the company successfully developed a new ozone-water based single wafer process chemistry which does not damage low k dielectric materials such as Black Diamond (TM), and does not corrode copper. In phase I this process achieved an etch rate greater than 8,000 A /min. The phase II research will concentrate on the early integration of the process hardware and process technology into a commercial single wafer spin processing system, the further development of process capabilities using 300 mm customer wafers, and the placement of three systems at customer sites for evaluation. Commercially, the successful completion of this research program will culminate in the development of a new single wafer process technology for use in the manufacture of the high-density semiconductor devices with feature sizes below 90 nm. Nearly all of the new manufacturing capacity is built for 300 mm wafer fabrication at the leading edge technology node. In addition to direct sales of $60 to $120 million per year of new wafer processing equipment incorporating this technology, this project will enable the productivity benefits and reduction in unit manufacturing costs provided by the early migration to the next technology node. In addition, the innovative copper compatible cleaning chemistry developed here holds promise for corrosion free cleaning and surface treatment of copper in other electronic device manufacturing applications. Finally, this process uses an environmentally benign "green" chemistry.

Technology keywords

Not reported

Agency intelligence

National Science Foundation

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