Very Dense, Low Power, Radiation Hardened, Nonvolatile Memory on SOI

"The objective of this proposal is to demonstrate the feasibility of producing very dense, radiation-hardened, low-power ferroelectric semiconductor memory for nonvolatile data storage in spacecraft, such as the SBIRS-Low. The approach to be demonstratedin this proposal is to use a one-transistor ferroelectric memory cell technology, the feasibility of which was demonstrated in a prior BMDO SBIR program, coupled with silicon-on-insulator (SOI) CMOS technology. The one-transistor memory cell can provide avery high memory density comparable to Flash memory, and fabrication on SOI can provide higher levels of radiation tolerance, particularly for SEU events. Fabrication on SOI may also provide an additional degree of freedom for decoding the memory withoutdisturb of deselected memory cells in harsh environments. Phase II is proposed to be fabrication and characterization of an SOI test chip and Phase III proposes to use a sponsor to apply the technology in a product to meet BMD needs. While Flash memorycan provide the nonvolatile memory densities required for many aerospace applications, it is fundamentally not radiation tolerant. Even with shielding, Flash memory cannot meet many radiation requirements. One-transistor ferroelectric memory celltechnology coupled with SOI can provide very high density and very high levels of radiation tolerance without shielding. The use of this technology can have an important major impact on stra