Ultra-Low-Power Digital CMOS for Multichip Modules

Space Computer Corporation, in collaboration with Stanford University, proposes to reduce power dissipation in CMOS digital integrated circuits by up to two orders of magnitude. Since power dissipation constitutes a major limitation to increased circuit density in electronic systems, such reduction is mandatory if the potential of 3-d multi-chip module packaging for minimizing size, weight, and power is to be realized. Our basic approach minimizes the switching energy per operation by reducing the supply and threshold voltages from five volts to one-half volt. In order to implement this approach, which involves the use of very small switching voltages, two key problems must be solved: compensation of statistical threshold variations over the surfaces of the chips, and reduction of power supply switching noise. We have devised several techniques for adaptively controlling the threshold voltage by tuning the substrate bias of each well in which a large block of gates is fabricated. We have also developed a variety of packaging and interconnect techniques for noise reduction, including the use of special shielding structures and area-array chip attachments. In Phase II we will design, fabricate and demonstrate a real-time FFT computation engine using ultra-low-power CMOS and advanced multichip module technology. The engine will have an equivalent throughput of 30 GOPS and a power consumption of 1.0 watt. In unpackaged form, it will occupy a volume of only 2.0 cubic centimeters and weigh only 4 grams.