Low-Power, Real-Time, Image Encoder Based on Vector Quantization

We propose to develop a low power image encoder based on vector quantization and active-pixel-sensor technology for real-time video, data compression. The hardware incorporates a novel pipelined architecture with intraframe and interframe block codings for significant bit-rate reduction and low-power operation. The intraframe coder utilizes vector quantization (VQ) for a low-loss video compression at 0.5 bit/pixel rate. The interframe coder employs an adaptive index replenishment scheme for further bit-rate reduction. Two candidate VQ architectures are proposed: (1) a full search VQ for a fully parallel, analog implementation with very low power dissipation and low chip count; (2) a tree search VQ for a pipelined, digital implementation with high configurability and low power operation. Active pixel sensor (APS) technology will be used to produce a low power, high resolution imager with on-chip pixel block formatting capability. In Phase 1, we optimize VQ architectures, perform preliminary design of an image encoder based on the selected VQ architecture, and develop APS devices for a Phase 2 hardware prototype development and demonstration.