AN ASSOCIATIVE NEURAL NET INTEGRATED CIRCUIT WITH ON-CHIP LEARNING

MICROEXPERT PROPOSES TO BUILD AN ARAM FOR TRUE ASSOCIATIVE RECALL THAT COMBINES PROCESSING AND LEARNING ON A SINGLE INTEGRATED CIRCUIT CHIP. DURING PHASE I WE WILL EVALUATE SEVERAL RELEVANT NEURAL NETWORK PARADIGMS, EXOTIC MATERIALS, DEVICE TYPES, AND ARCHITECTURES. WE WILL MODEL THE STORAGE CELL IN SOFTWARE TO DETERMINE SUCH CIRCUIT PERFORMANCE PARAMETERS AS ACCESS TIME, RETENTION TIME, AND DYNAMIC RANGE/ERROR CHARACTERISTICS. IN PHASE II WE WILL IMPLEMENT OUR DESIGN IN INTEGRATED CIRCUIT FORM, TAKING ADVANTAGE OF STANDARD SEMICONDUCTOR PROCESSING CAPABILITIES FOR LOW COST. OUR PERFORMANCE GOAL WILL BE 10(11) - 10(12) INTERCONNECTS/SEC. SINGLE CHIP, ONCHIP LEARNING CAPABILITY COMPRISES THE MAJOR INNOVATION OF THE PROJECT, THOUGH SOME OF THE CIRCUIT DESIGN TECHNIQUES REPRESENT ANOTHER LEVEL OF NOVELTY. MICROEXPERT WILL BE SUPPORTED IN THIS ENDEAVOR BY SAIC, WHICH IS DEVELOPING A SIMILAR SINGLE ON-CHIP LEARNING IC.