SBIR Phase II: VLSI Clocking Using BDS Technology

This SBIR Phase II research project intends to demonstrate a unique circuit method for GHz clock distribution inside CMOS chips, which provides state-of-the-art performance and is modular, scalable, and reusable. The theoretical foundation of this technology is the Bi-Directional Signaling (BDS) principle implemented over on-chip transmission lines. The project covers the design, fabrication, and evaluation of a comprehensive test chip aimed at validating key aspects of this new method such as the practical accuracy of a long distribution system, the realization of inexpensive high-quality integrated transmission lines, and the design of low power high precision active circuits for local clock generation. If laboratory tests confirm the expected performance and features, this method will be the basis of a valuable new VLSI Very Large Scale Integration (VLSI) technology. The demonstration of scalable and reusable circuit Intellectual Property (IP) for clock distribution will cause a major simplification in the VLSI design methodology with substantial benefits to the manufacturers of integrated circuits. The semiconductor industry will be able to produce faster processing, lower power, and lower cost VLSI components for systems such as computers and communication devices.