SYNTHETIC APERTURE RADAR (SAR) ENHANCING TECHNOLOGIES

There is a critical need for an all weather capability to detect and classify military targets using high resolution synthetic aperture radar (SAR) imagery. In many applications major difficulties arise because of the radio frequency interference (RFI) sources which can inadvertently or intentionally interfere with the operation of the SAR. Homogeneous processor architectures currently used to accomplish the real time SAR processing are ill equipped for the RFI mitigation function. Field Programmable Gate Arrays (FPGA) and block floating point (BFP) devices have demonstrated substantial throughput (up by a factor of 10), size, weight, and power advantages over central processing units (CPU) such as the Power PC while maintaining wide dynamic range (>120dB). Combining these specialized processing devices with general purpose CPUs into a heterogeneous processor has been shown to be feasible. Therefore, Integrated Sensors, Inc. (ISI) proposes to design an efficient COTS based heterogeneous parallel processor architecture and processing element optimized for real-time RFI detection and rejection. Representative hardware components, such as SHARP's BDSP 9124 block floating point device and special purpose field programmable gate arrays (FPGA), will provide the basis of the proposed processing element.