COMPUTER ARCHITECTURE/VERY HIGH LEVEL LANGUAGE DESIGN FOR BATTLE MANAGEMENT

A STUDY OF THE EFFICIENCIES AND ENGINEERING TRADE-OFFS INTEGRATING REDUNDANT NUMBER SYSTEM WITH SYSTOLIC ARRAY PROCESSING ELEMENTS IN ORDER TO CAPTURE THE INHERENT FAULT TOLERANT PROPERTIES OF SIGNED DIGITS IS PROPOSED. USING SIGNED DIGITS REDUCES CARRY/BORROW DISTANCE TO A MINIMUM THUS REALIZING HIGHLY MODULARIZED AND COLUMNAR ARITHMETIC ENGINES. PROCESSING CELLS BECOME REGULAR WITH FEWER INTERCONNECTIONS BETWEEN CELLS, THUS REDUCING VLSI WIRE INTERCONNECT SPACE. YIELDS INCREASE AND LESS POWER IS NECESSARY. FAULT TOLERANT AND MORE RELIABLE CIRCUITS ALSO RESULT BECAUSE OF THE REGULAR YET SIMPLER PE'S. LESS INTERCONNECTS AND SIMPLER CIRCUITS MAY RESULT IN HIGHER RAD HARDENING YIELDS.