LIFETIME MEASUREMENTS FOR ROUTINE QUALITY CONTROL/ASSESSMENT OF SEMICONDUCTOR WAFERS

We propose to continue our development of a non-invasive probe of the electrical quality of semiconductor wafers. This technique can be used to screen wafers or to ascertain total impact of specific process steps; it may serve as a routine qualification of some processes. Modern manufacturing technology requires an increasingly detailed statistical summary of the impact of processes on devices. Non-invasive techniques that can probe samples without interfering with a process line operation are crucial in this goal. We have already implemented this minority-carrier lifetime measurement to characterize Silicon-on-Insulator (SOI) samples as thin as 50 nm. We propose to extend the performance to shorter lifetimes (permitting more and thinner materials to be studied) and to smaller regions (permitting use as a monitor of product wafers). In addition, we intend to improve existing technology to permit rapid and routine operation. While useful for many materials this technique has proven especially useful in studies of SOI materials, since the superficial silicon films are electrically isolated from the substrate and therefore more difficult to characterize even by standard invasive techniques.