Ultra High Speed Processor

This proposal advances an approach to a processor that contains 4 to 64 reconfigurable DSPs/Neuro chips individually rated at 1.2-1.8 GigaFLOPS (10-15 BOPS) capable of operating in parallel and providing 5-7 .8 GigaFLOP performance for image processing applications. These parallel rDSP chips possess large associated internal memories (4-16 MBytes/chips) to support the processing of large sections of individual images. A revolutionary innovative architecture has been designed for developing parallel systems in the range of 1.2 GigaFLOPS to several TeraFLOPS. These can be achieved due to utilization of a new technology of DSP and reconfigurable parallel systems architecture design based on analysis of algorithmic and structural peculiarities of the given problem field. This technology was successfully used for production of a few generations of 32-640 parallel DSPs processors PS2000 and PS2100, broadly employed for processing of hydroacoustic and radar information, information from satellite, in geophysics, military and for solutions of large-scale scientific problems. The high performance parallel workstations with performance of at least 20 GigaFLOPS, 2 Gigabytes of RAM processed images, contains 5,000 x 4,000 one byte pixels with resolution of 500 pixel per inch in real time and 500 more stored.