Low Loss Vertical Light Guiding

The demand for photonic integrated circuits (PICs) encompasses a broad range of applications, from telecommunication and short-range interconnects to celestial navigation and atomic timing. However, with their complexity increasing, monolithic integration of all PIC components onto a single chip is becoming less feasible. There are many reasons behind this, ranging from the incompatibility of different CMOS technology nodes to the decreased yield as chip size and complexity increases. Therefore, the widescale adoption of PICs is dependent upon robust, densely packaged, efficient, and high throughput integration of several PIC chiplets into one co-packaged device. Current edge coupling and grating coupling (GC) solutions fall short of these requirements due to various factors, including high coupling loss, low spectral bandwidth, labor-intensive alignment and highly specific use cases. Mirrors, that reflect in-plane light into the vertical direction, have recently emerged as a broadband and low loss alternative. However, due to the fact that the vertical beam is unguided, their implementation has been limited to a narrow set of applications.To address the limitations of current couplers, RMD Inc. proposes a novel strategy which leverages the broadband low loss nature of reflector-based couplers and the unparalleled capabilities of atomic layer deposition (ALD) to provide chip-to-chip coupling between various material platforms and across large vertical distances. This innovative solution is accomplished through the integration of ALD deposited vertical waveguides in a CMOS compatible process. These vertical structures will provide long distance low loss guiding throughout the chips and enable direct chip-to-chip coupling with increased tolerance for misalignment. Light will be efficiently coupled between vertical waveguides and planar PICs using a spot size converter-mirror joint. Chip-to-chip self-alignment and bonding will be accomplished using CMOS compatible bump bonds. RMD Inc.’s proposed solution will enable low loss, self-aligning, and broadband vertical chip-to-chip coupling in a CMOS compatible process.