Photonic Crystal Chip-scale Optical Networks

As the clock speeds of integrated circuits continue to increase, the technological limits of all-electrical interconnects are becoming the overwhelming limit to system performance. In particular, over 80% of the latency in current ICs is due tointerconnect limitations. Moreover, current processors are requiring operational powers in excess of 100 Watts with I/O, on-chip interconnections, and clock distribution accounting for nearly 60% of the consumed power. Alas, this is expected to increaseto 70% in the near future. And, according to the current ITRS (International Technology Roadmap for Semiconductors) there are currently no known solutions for these problems. While optical networks/interconnects have been long proposed, their use on thechip-scale has been limited due the incompatibility of optical device materials and disparate integration scales, in comparison to electronic device materials and scales. Thus, to overcome this limitation we will demonstrate a photonic crystal technologythat uses the same materials and achieves the same, or better, scale of integration, while demonstrating a chip-scale photonic crystal network! From a DoD perspective, the successful demonstration of this technology will allow for faster processors forimplementing such algorithms as automated target recognition, high bandwidth communications, and secure encoded communication protocols. To this end, the objective of this Phase I proposal is to study and evaluate the ability to integrate nano-photonicdevices directly with CMOS electronic circuits and systems in such a way as to enable chip-scale photonic crystal networks. In addition, a final deliverable will be the formulation of an effective Phase II strategy for demonstrating the proposedtechnology. Commercial applications of this research and development include integrated circuit applications, commercial and military communication systems, and sensors.