Noise Tolerant Magnetoelectronics

CMOS digital logic is inherently noisy; generated noise can couple chip components through ground planes, power connections, and signal lines. Noise upsets are being exacerbated by the lower operating voltages and shrinking logic-level margins accompanyingsmaller feature sizes; measures to counter these effects are losing ground. The proposed project will demonstrate inherent properties of all-metal (no semiconductors) circuits based on the transpinnor, an active device with logic and amplificationcapabilities, that mitigate sources of noise: no spikes from digital switching; margin independence of feature size. The project objectives are to identify and characterize mechanisms underlying noise generated by analog and digital circuits; analyzeeffects of such noise on analog, digital, and mixed-signal circuits, for both all-metal and CMOS technologies, due to coupling between neighboring components; compare these effects in the two technologies; and provide a plan for system demonstrationincorporating the noise-abatement capabilities of transpinnor electronics. The proposed project is expected to demonstrate that all-metal circuit components can overcome the susceptibility of their CMOS counterparts to noise upsets in amultiple-noise-source environment, and that this advantage improves with decreasing feature size. All-metal electronics is an enabling technology that transcends applications.