WAVES Compiler/Generator for Optimum Performance and Transportability

IKOS Systems proposes to integrate a high performance, IEEE VHDL WAVES input-output capability into their VHDL mixed-level simulation environment. This will enhance WAVES ability to effectively support large, complex digital electronic designs. The interface will have two elements. First, a Compiler for WAVES data into a compact binary format for input into both the VHDL simulation engine and the gate level simulation accelerator inside the IKOS's VHDL mixed-level simulation environment. This will offer the user the choice of running IEEE WAVES within the VHDL kernel, or as a more efficient, compiled binary format that will be directly injectable into the simulation environment at run time. Second, a Generator that will output simulation result vectors in a WAVES data set format. This will improve the ease of WAVES creation, debug, and transport. These two mechanisms form the foundation for run time execution of IEEE WAVES simulation data within a commercially viable VHDL product that has the performance and capacity required for large and complex electronic system designs. The Phase I objectives are to validate the technical feasibility of this approach, and to produce the preliminary design concepts for the WAVES Compiler and WAVES output generator.