Testing Methodology/Tools for Asynchronous Circuits

"Theseus Logic intends to develop a test and verification tool and methodology that will provide the means to automatically insert testability into clockless circuits. Success in this endeavor will eliminate one of the remaining obstacles that hinderwidespread adoption of asynchronous design approaches for DoD and commercial applications.Such circuits have been demonstrated to have commercially valuable properties, including high performance, low noise/low EMI, low power and easy circuit composability.This Phase I proposal will involve the initial development of the algorithms and approaches for the methodology/tool. Emphasis will be placed on maintaining compatibility with existing commercial EDA tools. The potential benefits of clockless design are legion: increased performance, better power management, reduced power rail noise, reduced radiated EMI, robust operation, ease of integration, and increased design reuse are but a few of the potentialbenefits that have been demonstrated by companies and researchers working in the field. Yet industry has failed to adopt clockless techniques in more than an exploratory fashion. Why? Electronic Design Automation (EDA) tool support for clockless designsare the main stumbling block today. The clockless industry is caught in a chicken-and-egg scenario. Industry will not adopt clockless technology until commercial grade design tools become available; yet commercial EDA companies will not develop