SBIR/STTR Research Award
A Physical Artifact for the Improved Accuracy of Wafer Level Critical Dimension Measurements
Award amount
$50,000Program and phase
SBIR · Phase IAward year
1995Award details
- Awarding agency
- Department of Commerce
- Branch
- Not reported
- Recipient company
- Vlsi Standards, Inc.
- Proposal award date
- Not reported
- Contract end date
- Not reported
- UEI
- Not reported
- Solicitation number
- Not reported
- Topic code
- Not reported
Research abstract
The National Technology Roadmap for Semiconductors presents guidelines for 0.25 um devices by 1998, with 0.18 um geometries following in 2001. In order to meet this goal from a metrology standpoint, accurate and precise physical linewidth calibration artifacts must be developed. Currently, the only calibration artifacts commercially available are a 0.9 um reflected light standard (manufactured by VLSI Standards, quartz or wafer mounted) and a 0.5 um transmitted light standard from NIST (SRM 473).
The intent of this Phase I proposed study is to provide a methodology to manufacture and characterize linewidth standards in the range of 0.40 and 0.35 um, with extendibility to 0.18 um by the end of the decade. A detailed feasiblity analysis would outline the characterization process which would be accomplished by a two-pronged approach: 1) under an already existing NIST CRADA (Cooperative Atomic Force Microscope (C-AFM) would be employed for certification of the linewidth. 2) As an adjunct measurement tool, anle-resolved light scattering (ARLS) would be used to determine linewidth. This method could also employ a "first principles" traceability path to NIST based on the wavelength of the laser employed.
Technology keywords
Not reported