HIGH-SPEED SELF-TESTING MICROPROCESSOR FOR SPACECRAFT APPLICATIONS

THIS PROJECT CONCERNS A NOVEL MICROPROCESSOR STRUCTURE CAPABLE OF PERFORMING ARITHMETIC AND LOGIC OPERATIONS AT A HIGHER SPEED THAN PRESENTLY AVAILABLE MICROPROCESSORS. MOREOVER, THE NOVEL STRUCTURE APPEARS TO OFFER SIGNIFICANT ADVANTAGES FOR RADIATION HARDENING AND BUILT-IN SELF TESTING. SEPARATE SOLUTIONS FOR IMPROVING THE SPEED, RADIATION TOLERANCE, AND SELF TESTING OF A MICROPROCESSOR ARE KNOWN BY MOST DESIGNERS OF SPACECRAFT ELECTRONICS. HOWEVER, IT APPEARS THAT A SOLUTION CAPABLE OF SATISFYING ALL THREE REQUIREMENTS SIMULTANEOUSLY IS NOT AVAILABLE. THEMAIN OBJECTIVE IS TO PROVE THAT THE STRUCTURE OPERATES FASTER THAN PREVIOUSLY KNOWN MICROPROCESSOR STRUCTURES, THATIT IS INHERENTLY TOLERANT TO RADIATION, AND THAT IT FACILITATES BUILT-IN SELF TESTING. THE FIRST PART OF THIS WORK IS DIRECTED TOWARD A GREATER UNDERSTANDING OF HOW TO DESIGN HIGH SPEED MICROPROCESSORS AND TO EVALUATE QUANTITATIVELY THE PERFORMANCE OF THE STRUCTURE BY DEVELOPING A 16-BIT ARITHMETIC AND LOGIC UNIT, AND A REGISTER ARRAY. THE SECOND PART IS AN EFFORT TO DETERMINE HOW TO DESIGN RADIATION TOLERANT ARITHMETIC AND LOGIC UNITS,AND REGISTER ARRAYS. IT INVOLVES THE DEVELOPMENT OF TWO DIFFERENT TYPES OF DATA PATH RADIATION TOLERANT STRUCTURES TO COMPARE THEIR WORST CASE DELAYS. THE THIRD PART OF THE WORK ENHANCES KNOWLEDGE OF DESIGNING SELF TESTING DATA PATH STRUCTURES BY DEVELOPING A FAULT SIMULATOR FOR THE DATA PATHTO DETERMINE AN OPTIMUM SELF TEST SEQUENCE. THIS APPROACH APPEARS ABOUT 30% FASTER THAN PRESENTLY KNOWN MICROPROCESSORS.