ARCHITECTURAL STUDY OF A DSP MULTIPROCESSOR CONCEPT

EMERGING DIGITAL SIGNAL PROCESSING (DSP) VLSI PRODUCTS ARE WIDENING THE HORIZONS OF SYSTEM DESIGNERS. BECAUSE OF THEIRCOMPACT SIZE AND LOW COST, TIGHTLY-COUPLED SINGLE-BOARD MUTLIPROCESSOR CONFIGURATIONS ARE NOW QUITE FEASIBLE. THIS STUDY WILL EXAMINE THE DEGREE TO WHICH HARDWARE CAN BE MINIMIZED BY JUDICIOUS SELECTION OF AN ARCHITECTURE THAT LENDS ITSELF TO MODERN VERY LONG INSTRUCTION WORD (VLIW) COMPILATION TECHNIQUES. WITH THE NEED TO SOLVE DSP PROBLEMSIN MIND, THE ARCHITECTURAL TRADEOFFS WILL FIRST BE DETERMINED FOR A SMALL NUMBER OF CRITICAL DSP ROUTINES INVOLVING FFT'S, 2D FILTERING, AND DYNAMIC PROGRAMMING ALGORITHMS. IN THE LATER STAGES OF THE STUDY, AUTOMATIC INSTRUCTION SCHEDULING/COMPACTION TECHNIQUES WILL BE RELATED TO THE ARCHITECTURAL CHOICES. ULTIMATELY, IT IS EXPECTED THAT THE RESULTS GENERATED WILL HIGHLIGHT THE STRENGTHS AND WEAKNESSES FOR SOME OF THE COMMERCIALLY-AVAILABLE DSP CHIPS.