Compact Electro-Optic Modulators Based on Barium Titanate on Silicon Platform

The primary goal of this proposal is to deliver an ultra-compact, energy efficient, wide band electro optic modulator (EOM) based on SOI-integrated BaTiO3 (BTO) and establish the manufacturing capability for a materials platform to become standard for fabricating high-speed, small footprint, low-power EOMs in co-packaged optics and optical network-on-chip technologies. In Phase I we have considered two types of EOMs, the micro ring modulator (MRM) and Mach-Zehnder interferometer (MZI), both hybrid and monolithic approaches were considered. We have demonstrated very high-quality single crystal BTO films on SOI of up to half a micron in thickness and ability to control strain and crystallographic orientation of such films. BTO boasts one of the largest Pockles coefficients known (1,300 pm/V), enabling fabrication of ultra-efficient compact phase shifters. We have built compact (150-450 mm in size) monolithic modulators with low V?·L. We demonstrated waveguide exhibiting low optical loss on the order of 0.2 dB/cm and strong electro optic effect and MRMs with quality factors of 140,000 with radius of 50 mm. Our goal is to optimize EOMs under 100 mm in size, with V?·L of about 0.2 V·cm, 0.2 dB/cm loss, and operating at high frequencies at the telecom wavelength of 1.55 um. The Phase II Base period effort will determine the technical feasibility of creating large area (~cm2) single domain a-axis-oriented BTO, where the ferroelectric polarization is in the plane of the film. Having devices built on single domain BTO will double the EO response and make the modulators even lower power or smaller footprint. At the same time, we will optimize the modulators for high-speed operation, initially to 20 GHz but ultimately to beyond 40 GHz. For the Phase II Option period, we will turn our device efforts towards understanding the temperature dependence of BTO-based modulator performance, and heterogeneous integration of III-V electro-optic devices (sources and detectors) with BTO-based photonic circuits. At the same time, we will scale up the BTO on Si process to 200-mm wafer. We will study material uniformity, surface flatness, stress management and wafer curvature issues arising from large area thin film growth. This will result in a roadmap to fully integrated photonic integrated circuits or PICs based on commercial size Si-integrated BTO platform.