SBIR/STTR Research Award
A Parallel Design Tool for the Automated Life Testing and Analysis of Dependable Computing Systems
Award amount
$79,119Program and phase
SBIR · Phase IAward year
1995Award details
- Awarding agency
- Department of Defense
- Branch
- Air Force
- Recipient company
- Reliable Computer Technology
- Proposal award date
- Not reported
- Contract end date
- Not reported
- UEI
- Not reported
- Solicitation number
- Not reported
- Topic code
- Not reported
Research abstract
The primary objective of this Phase I research is to develop a tool for evaluating the dependability of fault-tolerant computing systems. Dependability has traditionally been evaluated through combinatorial and Markov modeling. These analytical techniques have several limitations which can restrict their applicability. Simulation avoids many of the limitations, allowing for more precise representation of system attributes than feasible with analytical modeling. However, the computational demands of simulating a system in detail, at a low abstraction level, currently prohibit evaluation of high level dependability metrics such as reliability and availability. The new approach abstracts a system at the architectural level, and employs life testing though simulated fault-injection to accurately and efficiently measure dependability. Based on an existing tool, called the REliable Architecture Characterization Tool (REACT), the new tool will incorporate parallelism and variance reduction techniques to reduce execution time and enable the affordable analysis of computing systems with ultrahigh reliabilities (R(t)>1 - 10 -9).
Technology keywords
Not reported