Advanced Modeling of Silicon-on-Insulator Devices for Low Power Electronics

With power consumpition becoming prohibitive, SOI has become a key technological approach for production of integrated circutis with markedly reduced power requirments. SOI provides improvement (maintenance) of circuit performance and reduction of power consumption, largely independent of circuit architecture. Improved modelilng is a way of reducing the escalating cost impact of technology and product developments. Various parallel (some redundant) projects are focused on model development for particular types of SOI devices, but no comprehensive SOI circuit design models are readily available commercially. It is the purpose of this project to compare the modeling approaches for SOI devices, determine suitability for circuit level modeling which provides power estimation and parametric analysis for [low] power optimization, examine tradeoffs in efficiency and [power consumption predictive] accuracy, develop or modify models as required, and apply the model to test circuits to estimate power reduction. One or more commercial vendors will be involved for transfer of results to commercially available circuit design software. Key aspects of the desired modeling approach will be: comprehensiveness of device modes and types, applicability to perform parameter optimization, and inclusiveness of key SOI parameters for low power level estimation. Device data will be used for model verification. ANTICIPATED BENEFITS: The project will provide a needed design tool for SOI circuits, which can be expected to promote SOI technology use. Sensitivity to technology parameters will be identified to optimize power reduction, analyze cost tradeoffs, and design Phase II experiments. The ultimate goal of the project is installation of useful SOI CMOS LPE design. Ibis's involvement in this effort will enhance technolgoy transfer.