SBIR/STTR Research Award
HIGH DATA RATE STORAGE OF DATA
Award amount
$748,283Program and phase
SBIR · Phase IIAward year
1998Award details
- Awarding agency
- Department of Defense
- Branch
- Office of the Secretary of Defense
- Recipient company
- SHAWN SYSTEMS, INC.
- Proposal award date
- Not reported
- Contract end date
- Not reported
- UEI
- Not reported
- Solicitation number
- Not reported
- Topic code
- Not reported
Research abstract
We propose to design a state-of-the-art high speed solid-state data recorder with 200 Gbyte capacity (exceeding the required 500 to 1500 Gbit or 63 ~ 188 GBytes capacity). Data can be stored at 10 Gbps (1250 Mbytes/s), with a corrected bit error rate less than 1 bit in 1014. The 100 W, and occupy less than 1.5 cu. ft.The proposed design will make extensive use of COTS parts. The storage controller will initially be simulated to verify correctness. We then will use FPGAs for in-circuit emulation, and finally tape out to silicon for the ASIC.We make extensive use of digital signal processing to condition the incoming digital, and converted analog data streams; compact the data using lossless (or lossy, depending upon the criticality of the data and end application) data compression algorithms; and store it with error correction and error detection codes. We can also incorporate fault tolerance, and offer different architectures to suit varying levels of dependability and reliability that cannot be matched by tape systems. Our team brings tremendous expertise in high speed data acquisition, digital signal processing and hardware design, and has built 3 generations of machines at Digital Equipment Corp.
Technology keywords
Not reported