Computer-Assisted High-speed Stimulus Pattern and Timing Set Generation

This proposed effort describes the development of an algorithm that will aid theengineer in determining timing set and digital pattern attributes in the developmentof a digital test program. This algorithm will automate the process of examining thethousands of different signal variations and patterns that are possible in a typicaldigital test program, and develop optimized high-speed timing sets and stimuluspatterns using knowledge of the types of problems endemic to such applications.This includes knowledge of components, circuit propagation delays, and other factorsboth internal to the UUT and external to the ATE. The resulting software isanticipated to provide a comprehensive set of tools to assist the engineer indeveloping the best possible digital test program.The proposed technology is anticipated to increase the accuracy and effectiveness oftest programs for digital electronics, reducing or eliminating many of the re-testOK and cannot duplicate conditions currently found in existing test programs.Commercial potential for this technology exists in production test and softwaredevelopment tool applications.