SBIR Phase I: A Low Cost Semiconductor Metallization-Planarization Process

This Small Business Innovation Research (SBIR) Phase I project will demonstrate the feasibility of an innovative process for copper metallization and planarization of semiconductor scale features. In contrast to geometric leveling or true leveling in the presence of levelers and brighteners, the proposed electrochemical deposition process is based on charge or Faradaic mediated leveling. The current copper metallization process utilizes a difficult to control plating bath containing levelers and brighteners and generates between 30 and 50 liters of waste slurry for each 8-inch wafer processed. The proposed charge modulated electrochemical deposition process will operate in a simple, easily controlled plating bath and will eliminate or substantially reduce the waste and cost of the current chemical/mechanical-processing step. During the Phase I program, the theoretical basis for the Faradaic mediated leveling process will be established and validated using state-of-the-art ULSI wafers. It is anticipated that the Faradaic mediated leveling process will eliminate or substantially reduce (i.e., by greater than 85%) the copper waste slurry and provide substantial cost savings relevant to the state-of-the-art copper metallization processes in the semiconductor industry