Very-High-Speed Integrated Circuit Hardware Design Language (VHDL) Behavioral Simulation Acceleration Engine

MTL proposes to perform the preliminary design for a very high speed integrated circuit hardware design language (VHDL) behavioral simulation acceleration engine, and to demonstrate the critical aspects of that design though simulation. The approach will be to use the QUEST parallel simulation technology developed at the University of Cincinnati which currently executes on a general purpose distributed processor architecture to greatly speed up simulation execution. Data obtained through instrumentation of the QUEST simulator will be used to identify the necessary computer architecture, including memoey structures, general-purpose and coprocessor execution units, input/output architecture, inter- and intra networks, host interfacing, systems software, and application software necessary to significantly accelerate VHDL simulation over that possible even in general aspects purpose parallel computers. As a part of design effort, critical aspects of the design will be identified, simulated, tested and demonstrated to ensure a low-risk high-performance implentaton of IEEE/ANSI 1076 VHDL simulation. high-performance implementation of the IEEE/ANSI 1076 VHDL simulation.