Real Time COTS Chip for Unified Avionics Interconnect

This proposal covers the first phase of three work phases: Phase I: a) study the Serial Express and SCI-RT protocols, b) develop the adaptations necessary for real-time applications, c) simulate them, d) choose the best protocol, e) determine the requirements, feasibility, and cost of standard cell and a prototype ASIC design, and f) determine the basic requirements, feasibility and cost of a VMEbus-based SCI/SX bridge, as a demonstration vehicle; Phase II: Design a standard cell ASIC component, prototype chip, and VMEbus-based SCI-RT/SX bridge; Phase III: Transition the standard cell and prototype ASIC designs to a commercial chip fabricator for production. Phase I work will take advantage of previous or current work, done by Interconnect Systems Solution and Edgewater Computer Systems, Inc.: ISS has designed commercial SCI chips and is about to complete a SX chip design. ISS will be responsible for Phase I items d), e) and f), above. ECSI wrote the original proposed SCI-RT draft specification and was key in starting the SCI-RT Working Group. ECSI is currently carrying out a study of the SCI-RT and SX protocols, for the Navy, which will be the basis for Phase I items a), b), c), d) and f), above.