Multi-Chip Integration

The resolution gap between available chip (sub-micron) and off-chip (100 to 125 micron) will be closed by a new laminate interconnection technology. Semiconductor manufacturing techniques, either on wafer (NChip) or in thin film form (IBM and others), are used to bring line widths and thicknesses into this resolution gap forming 10 micron lines. Problems with this technology include low yields, limited substrate size, a limited number of interconnect layers, and high interconnect sheet resistance. Nonetheless, some products are being produced using this technology (e.g., the Tadpole Unix compatible notebook computer). Semiconductor manufacturing techniques will be adapted to a new process for making laminate interconnects, controlled by proprietary in-situ for in-line process control, which will produce large ares fine lines and spaces with semiconductor reliability. Capital and product costs will be low like the PWB industry. The process provides: (1) Density of 1100"/sq. inch with 45 micron vias with up to 20 layers on laminates which can be 50 cms square with sheet resistances of less than .001 ohms/square. (2) Uniform wires and controlled impedances made by employing fast rate close proximately micro deposition. (3) Direct digital lithography. (4) Hazardous waste reduction of over two million tons annually if used ubiquitously. Anticipated Benefits: This project will enalbe better MCMs to be produced with: 1) Larger are/most chips; 2) Lower cost controlled impedance interconnects; 3) Better use of seperate technologies; 4) Interconnects made with new technology and proven semiconductor methods; 5) Laminate interconnects with 15 micron features and 45 micron vias.