Digital Data Rate Interpolator and Modulator

The existing GC2011 digital filter chip provides 2.56 billion 14 bit by 14 bit, multiply-accumulate operations per second. The chip provides 32 filter cells each of which contain a 14 by 14 multiplier, a 32 bit accumulator, a pre-adder/subtracter (for symmetric filters), and 4 memory cells each for data delay forward, backward, and coefficients. The chip operates at speeds up to 80 MHz. Additional support for real to complex or complex to real, decimation, interpolation, quarter, half and double rate modes is provided on chip. The chip also contains on board snapshot of RAM to support adaptive filtering. We propose to increase its interpolation capabilities from 16:1 to 20:1 and to increase the input data word size from 12 bits to 14 bits to satisfy the requirements MICOM Advanced Simulation Center. It is also possible that the chip can satisfy the system needs as is - though some changes to the requirements would be required. Finally, we present an idea for a new chip that would provide substantially greater capabilities.