Utilizing MIL-STD-1553B Digital Data Bus Devices Across an IEEE-1394A Serial Bus

In this first phase of technical development, this proposal for research and development seeks to design an architecture that will enable MIL-STD-1553B digital data bus monitoring through an isochronous channel of an IEEE-1394A High Performance Serial Bus.The traits of this design will give I&T (integration and test) and launch operations teams full access to the spacecraft avionics bus, including the ability to monitor both IEEE-1394 traffic as well as MIL-STD-1553 traffic. This development will allow operators to more reliably detect and analyze anomalous conditions from a remote location through a retractable umbilicus.The second objective of the first phase of this development is the design of a bridge, which will enable two-way data communications between the IEEE-1394A and MIL-STD-1553B buses. The design will implement the fault-tolerant architecture developed at the JPL Center for Integrated Space Microsystems.Technical challenges include maintaining the redundant nature of the MIL-STD-1553B digital data bus, maintaining signal timing requirements of MIL-STD-1553B, and encapsulating MIL-STD-1553B signals on an IEEE-1394A bus.If Phase I proves feasibility, Phase II will be proposed to develop a commercially viable system around this architecture and test its capabilities in a laboratory environment.