TAILORABLE HIGH THERMAL CONDUCTIVITY CTE MATCHED COMPOSITE CERAMIC CIRCUIT BOARDS

THIS PHASE I PROGRAM WILL DEMONSTRATE THE TECHNICAL VIABILITY OF DESIGNING AND MANUFACTURING INTEGRATED CERAMIC MATRIX COMPOSITE CIRCUIT BOARDS FOR A VARIETY OF ELECTRONIC DEVICES INCLUDING (HIGH POWER [25-50W] HIGH DENSITY [300 - 500 LEADS]). GRAPHITE FIBER REINFORCED CVI CERAMIC MATRIX COMPOSITE PLATES WILL BE FABRICATED WITH THREE FIBER VOLUME FRACTIONS (35, 40, 45%) USING REFRACTORY COMPOSITES', INC. NEW RECOMP COMPOSITE TECHNOLOGY. RECOMP MATERIALS ARE MECHANISTIC IN NATURE AS THE FIBER AND MATRIX SELECTION CAN BE TUNED TO MEET A VARIETY OF OPERATIONAL NEEDS. THIS PROGRAM PROPOSES THE DISTINCT POSSIBILITY THAT HIGH K, SILICON MATCHED CTE COMPOSITE SUBSTRATES CAN BE PRODUCED WITH THIS TECHNOLOGY. A SERIES OF PANELS WILL BE FABRICATED USING NEW HIGH K (2X COPPER) PITCH FIBERS IN A SILICON CARBIDE MATRIX. DEMONSTRATION OF RF BARRIERS AND DIELECTRIC INSULATION LAYERS, HIGH DENSITY COPPER TRACES AND INTERCONNECT VIAS WILL BE CREATED USING CVD/PVD ADAPTATION OF RCI BACKGROUND TECHNOLOGY.EXISTING SEMICONDUCTOR MASKING AND ETCHING TECHNIQUES WILL BE ADOPTED FOR PROTOTYPE DEMONSTRATION PURPOSES. TECHNICAL ADVICE AND CONSULTATION RELATIVE TO DEVICE DESIGN, INTERCONNECT, ETCHING AND SYSTEM UTILITY DEMONSTRATION WILL BE PROVIDED BY MOTOROLA, INC., ADVANCED PACKAGING GROUP. A SIGNIFICANT TASK IN THIS PROGRAM WILL BE THE INITIATION OF PLANAR INTEGRATION DESIGN AND LAYER APPLICATION.