GENERATING PARALLEL DIGITAL HARDWARE SIMULATORS FROM RECURSION EQUATION SPECIFICATIONS

PREVIOUS RESEARCH HAS SHOWN THAT RECURSION EQUATIONS PROVIDE AN EXCELLENT COMPUTER HARDWARE DESCRIPTION LANGUAGE (CHDL). CURRENTLY THIS APPROACH IS NOT PRACTICAL BECAUSE IT PRODUCES SIMULATORS THAT ARE TOO SLOW. WE PLAN TO DEVELOP A METHOD FOR COMPILING ITERATIVE RECURSION EQUATIONS INTO AN EFFICIENT SIMULATOR PROGRAM IN THE C LANGUAGE, WHICH WILL LEAD TO PRACTICAL CAD TOOLS. WE ALSO PLAN TO INVESTIGATE COMPILING RECURSION EQUATIONS INTO PARALLEL SIMULATORS FOR COMMERCIALLY AVAILABLE MIMD COMPUTERS SUCH AS THE ALLIANT AND BUTTERFLY. THIS WORK WILL LEAD TO PRACTICAL CAD TOOLS THAT ARE FASTER AND EASIER TO USE THAN THE CURRENT ONES.